Moises Cases
Teaching Experience
Moises Cases has over 39 years of extensive progressive experience in very-large scale integration (VLSI) chip and package designs, in system level electrical and package designs, and in complex project and people management. He retired as a Distinguished Engineer from IBM System and Technology (STG) group in 2009. He was the team leader for system electrical design and integration of modular and blade servers and was responsible for signal and power distribution integrity, and system level timings for complex multiple board system designs. He obtained his Bachelor of Science in Electrical Engineering from City College of New York, NY in 1969, his Master of Science in Electronic Engineering from New York University, NY in 1973 and his Master of Science in Computer Engineering from Syracuse University, NY in 1979. Moises Cases was awarded IEEE Fellow grade in 2008 for contributions to design and noise control for power and signal distribution in digital systems and he is a member of the IEEE Fellows Committee from 2010 to 2014 and 2020-present. He is also a member of the IEEE Education Activities Board (EAB), The Continued Education Committee (CEC), and the Future Direction Committee (FDC).
Areas of Expertise
Signal and power distribution integrity, and system level timings for complex high-speed multiple board system designs; including memory and networking systems.
Modeling, simulation and verification of integrated circuits and systems designs and interconnect technologies with emphasis on high-speed and low powers systems
.High-speed interconnect design methodology and tools; including existing and emerging industry standards.
Digital circuits, digital chips, microprocessors, and electronic packages design, modeling and verification.
Digital system designs and I/O architectures.
Integrated programmable logic arrays and charge coupled devices.
CMOS and CCD process and device design, modeling and development.
Service science management and engineering applied to engineering services.
Teaching Experience:
Adjunct professor at Austin Community College in the Engineering Technologies department since 2010
Lecturer at IEEE SPI 2013, "Digital Memory Design for Packaging Engineers", Paris, France, May 2013
Lecturer at IEEE EDAPS 2012, "High Speed Serial links Design, Modeling, Simulation, and Measurements", Taipei, Taiwan, December 2012
Lecturer at IEEE EDAPS 2012, "Digital Memory Design for Packaging Engineers", Taipei, Taiwan, December 2012
Lecturer at IEEE EDAPS 2011 "Digital Memory Design for Packaging Engineers", Hangzhou, China, December 2011
Keynote speaker at IEEE SPI 2011, "Technical and Economical Challenges for Electronic Packaging Engineers", Naples, Italy, May 2011
IEEE mini-course instructor at ECTC 2010 on “Digital Memory Design for Packaging Engineers”, Las Vegas, NV, June 2010
Tutorial instructor on “High-speed Signal Integrity Design Challenges and Techniques” at EDAPS 2008, Seoul, Korea, December 2008
Invited speaker at National Taiwan University (NTU), “Embedded Capacitors in Laminate Substrates and PCBs for Server Systems”, Taipei, Taiwan, December 2007
Tutorial instructor on “High-speed Signal Integrity Design Challenges and Techniques” at EDAPS 2007, Taipei, Taiwan, December 2007
Organized and team conducted workshop on “Marketing Yourself and Interview Skills” at University of Texas at Austin, Austin, TX. April 2006
Invited speaker at Georgia Institute of Technology, “Electrical Modeling and Design Tool Challenges for Future Server Designs,” Atlanta, GA, September 2005
Presentations on Global and System Technology Outlooks at Georgia Institute of Technology and its Packaging Research Center, Atlanta, GA, 2004-2005
Invited speaker at Electrical Design of Advanced Packaging and Systems Symposium, “System Level Electrical and Packaging Issues for Server Designs,” Bangalore, India, December 2005
Tutorial co-instructor on “Signal and Power Integrity” at EDAPS 2005, Bangalore, India, December 2005
Invited speaker at Korea Advanced Institute of Science and Technology (KAIST), “Package Design Challenges for High Speed Systems”, Daejon, Korea, November 2003
Tutorial instructor on “System Packaging Design Challenges for High Speed Serial Links” at EDAPS 2003, Daejon, Korea, November 2003
Presentations on Global and System Technology Outlooks at Pennsylvania State University, October 2003
IEEE mini-course instructor at EPEPS workshops on “High-speed I/O Circuit Designs”, 2002-2005
Invited speaker at University of Puerto Rico at Mayagüez (UPRM), “System-on-Chip Design Challenges Using Deep Submicron CMOS Technologies,” January 2000
Course instructor at VLSI Workshop, Florida Atlantic University, Short Course on VLSI Design; conducted and published short course on FET/Bipolar Technologies for VLSI, March 1983
Professional Publications
Moises Cases has 96 patents filed and 95 refereed publications in various professional manuscripts and conferences. These patents and publications encompass numerous technical areas and fields of studies in integrated circuits and systems, interconnect technologies, interconnect design methodology and tools, digital system designs and I/O architecture, integrated programmable logic arrays and charge coupled devices, and service science management and engineering.
Mr. Cases has co-authored chapters in several books, such as “Introduction to Service Engineering” and “Design and Test for Multiple Gbps Communication Devices and Systems.
PATENTS AND PUBLICATIONS
96 U.S. Patents filed and 9 patents pending
54 IBM Technical Disclosure Bulletin Publications
95 External Refereed Technical Publications
45 IBM Technical Reports
Professional awards
Moises Cases was awarded IEEE Fellow grade in 2008 for contributions to design and noise control for power and signal distribution in digital systems. He received the IEEE CPMT Outstanding Sustained Technical Contribution Award in 2009, the Teacher-Engineer Partnership Award from IEEE in 2008, the Albert V. Baez Award from HENAAC in 2007, the Business/Community Representative of the Year Award from Austin Independent School District (AISD) in 2007, and the Hispanic in Technology Corporate Award from the Society of Hispanic Professional Engineers (SHPE) in 2006. He was elected to the IBM Academy of Technology in 2008. He is a member of Tau Beta Pi and Etta Kappa Nu honor societies. In addition, Mr. Cases has received the following awards and recognitions:
Corporate Business/ Community Representative of the Year Award from AISD in 2007.
STAR Award from SHPE: Hispanic in Technology Corporate Award in 2006.
IEEE Lifetime Fellow awarded in 2023.
IBM Master Inventor: 2006 – 2009
IBM Invention Achievement Awards: 26 Plateaus
IBM Authors Recognition Awards: 27 Plateaus
IBM Outstanding Technical Achievement Awards: 5 Awards
IEEE awards for outstanding contributions: 6 Awards (1999 – 2009)
Published: August 01, 2025