Lam Ta

Post-Secondary Education

University of Texas Austin
Bachelor of Science in Electri
Electrical Engineering

University of Texas Austin
Master of Science in Engineeri
Electrical Engineering

Post-Secondary Education (continued)

Rollins College, Winter Park, Florida

Master of Business Administration

Professional Affiliations

* BGS (Beta Gamma Sigma, Business Honors Society)

* HKN (Electrical Engineering Honors Society)

Professional Experience

Forty-five years of hands-on experience in Semiconductror Technology R&D, Design, Test, Device/Process Integration, Product Engineering, Wafer Fab, Assembly, and Failure Analyses. Successfully led teams to develop new technologies and products resulting in very high-volume production of several generations of microcontrollers. Have worked at Motorola, Harris Semiconductor, AT&T Microelectronics, SEMATECH, Freescale Semiconductor, NXP Semiconductor.  Distinguished Member of Technical Staff (DMTS) at Freescale, Technical Director at NXP.

Teaching Experience

Since November 2023, have taught CE class in Introductory and Intermediate Electronics, Sensors, Motor Control, PLC, Schematics, Semiconductor Processing, CMOS/FinFET for students at Tesla, Samsung, Applied Materials, Infineon, NXP Semiconductor.

Professional Publications

PATENTS AWARDED:

* Automatic High-speed Tristate Buffer (co-inventor)

* Low-power, Compact CMOS Comparator (co-inventor)

PUBLICATIONS (sample):

* Deployment of Custom Algorithms for Very High-Volume Quality Control, Yield Diagnostics, and Equipment Monitoring, International Test Conference Data-2014 Workshop (Co-author).

* MRAM Preps for Role in Embedded Memory, EE Times April 2007 (Co-author).   Article was translated into several languages.

* The Effect of PVD Ti Film Thickness and TiSi2 Interlayer Formation on the Stress of the Bonding Pad Poly Glue Layer, VMIC Conference, June, 97. (Co-author)

* Motorola Defensive Publication: Self-aligned Late NOR-Type ROM Programming Utilizing LDD Implant (Apr 97)           

* A 0.25um Fully Planarized CMOS Technology, ESSDERC 1993 (Co-author)

* An Advanced, Scaled Backend of the Line Dielectric Isolation Process, VMIC 1993. (Co-author)