Dan Boyne


Post-Secondary Education

Case Western Reserve University
Bachelor of Science
Physics

Ohio State University
Master of Science
Metallurgical Engineering


Teaching Experience

Assistant Adjunct Professor  •  Austin Community College (Austin, TX)  •  Jan 2019 to Present

  • Instruct introductory engineering courses to undergraduate students.

 

Physics Tutor  •  Austin Community College (Austin, TX)  •  Sep 2017 to Present

  • Tutor first- and second-year undergraduate students in physics and engineering.

 


Engineering Experience

Package Innovation Operations  •  NXP Semiconductors (Austin, TX)  •  Jul 2017 to Jun 2019

  • Responsible for tracking projects, budgets, headcount, and metrics for 250-person global R&D engineering organization.

 

Package Design Manager  •  Freescale Semiconductor/NXP Semiconductors  •  2015 to Jun 2017

  • Responsible for design and electrical modeling of integrated circuit packages for 32-bit mixed-signal ICs.
  • Managed 9 employees in Austin, Phoenix, Malaysia, Taiwan and China.

 

Package Technology Integration Manager  •  Freescale Semiconductor  •  2013 to 2015

  • Managed 12 employees in Austin and Phoenix responsible for developing new package technologies for 32-bit ICs, pressure-/motion-sensors, and 77-GHz radar products.
  • Achieved technology certifications for packages for 55-nm automotive ICs, 77-GHz radar products, and sensor products.
  • Refined manufacturing processes of ball-grid array, lead frame, and wafer-level packaging.

 

Package Electrical Modeling Manager  •  Freescale Semiconductor  •  2011 to 2013

  • Managed 5-person team that assessed electrical performance of package designs using 3D parasitic extraction tools to create s-parameter and SPICE models of packages.
  • Improved modeling throughput 25% using software automation while leveraging existing Linux infrastructure. Developed ability to generate package models using web interface.
  • Improved team’s capabilities with development of tools to streamline SPICE modeling of packaging effects on DDR signal integrity.

 

Failure Analysis Lab Manager  •  Freescale Semiconductor  •  2008 – 2011

  • Managed failure analysis (FA) activities for a variety of advanced CMOS technologies. Responsible for staffing, training, budget, and capital purchases for electrical and physical FA teams comprising 35+ Austin engineers and technicians.
  • Increased FA productivity 11% from 2008 to 2010 while decreasing costs 13%. Improved efficiency by streamlining inter-department transactions and standardizing processes.
  • Coordinated $21M of capital purchases for laboratory investments from 2006 to 2010. Worked closely with Asia, Europe, and US FA and reliability labs to prioritize and justify capital investments based on ROI and alignment with business requirements.

 

Failure Analysis Engineer and Section Manager  •  Motorola/Freescale  •  1996 – 2008

  • Performed IC failure analysis and supported yield improvement for CMOS microcontroller products. Isolated electrical faults and identified defects through physical analysis (microprobing, cross-sectioning, electron microscopy, etc.). Determined failure mechanisms for customer returns, internal qualification and yield failures. Interfaced extensively with Design/Product/Process Engineering to interpret FA findings and define corrective actions.
  • Developed and maintained infrastructure to support FA lab, including software for fault simulation, translation of digital test patterns, tester loadboards, lab’s web site, Unix file server and clients. Trained engineers in Austin and Phoenix to run LVS software from Cadence and Mentor to create IC layouts and cross-linked schematics.
  • Responsible for lab’s digital testers, including hardware troubleshooting and maintaining C software for generating test patterns. Provided on-site training in Asia’s FA labs for utilizing the testers and software. Defined software solution for translating digital test patterns from Agilent 93K platform to Credence’s STIL-based test platform.

 

Wafer Fab Device Engineer  •  Motorola (Austin, TX)  •  1993 – 1995

  • Implemented process and test enhancements to improve yields for high-volume semicustom product lines with run-rates of 1000 wafers/week. Analyzed electrical and failure analysis data to identify and eliminate root causes for poor yield.
  • Successfully transferred wafer manufacturing processes between fabs, with significant interaction with Product, Design, Test, and Manufacturing Engineering.

 

Reliability Engineer  •  IBM Corp. (East Fishkill, NY)  •  1988 – 1990, 1992 – 1993

  • Assessed reliability of advanced bipolar semiconductor devices for high-end mainframe computer systems. Modeled device reliability using lab results.
  • Generated recommendations for design, manufacturing and test engineers to improve reliability of VLSI products.

 


Professional Publications

Chu-Chung Stephen Lee, TuAnh Tran, Dan Boyne, Leo Higgins, Andrew Mawer, "Copper Versus Palladium-coated Copper Wire Process and Reliability Differences," Proceedings of the 64th Electronics Components and Technology Conference, p. 1539, 2014.

 

Burton Carpenter, Boon Yew Low, Leo M. Higgins III, Sriram Neelakantan, Robert Wenzel, and Daniel Boyne, "Thermally and Electrically Enhanced Wirebond BGA," International Symposium on Microelectronics, Vol. 2013, No. 1, pp. 478-483.

 

D. Boyne, J. Goertz, D. Parsons, "Test and Failure Analysis Implications of a Novel Inter-Bit Dependency in a Non-Volatile Memory," 23rd International Symposium for Testing and Failure Analysis, p. 25, 1997.

 

D. Boyne, "Epitaxy in Systems with Large Misfit in Lattice Parameter," Master's Thesis, Ohio State University, 1992.

 

D. Boyne, L. Hsia, R. Wachnik, R. Decker, and C. Wasik, "X-ray Radiation Damage and a Reliability Study on Bipolar Devices," Applied Physics Letters, v. 58, p. 2687, 1991.

 

D. Boyne, E.K. Tan and S.A. Dregia, "Misfit Dislocations in Multivariant Epitaxy of Silver on Copper," presented at the 1991 Electron Microscopy Society of America Conference, San José, California.

 

W.J. Tomasch, H.A. Blackstead, S.T. Ruggiero, P.J. McGinn, John R. Clem, K. Chen, J.W. Weber and D. Boyne, "Magnetic Field Dependence of Nonresonant Microwave Power Dissipation in YBa2Cu3O7-x," Physical Review B, v. 37, p. 9864, 1988.

 

D.E. Farrell, J.D. McGervey, Y. Kobayashi, W. Zheng, B.S. Chadrasekhar, and D. Boyne, "Positron Lifetime in YBa2Cu3O7-x," Bull. Am. Phys. Soc, v. 33, p. 804, 1988.

 

M.R. De Guire, C.J. Kim, W.-H. Lu, and D. Boyne, "Texture Development During Pressing and Sintering of YBa2Cu3O7-x." In: Man F. Yan, editor. Ceramic Superconductors II: Research Update, Westerville (OH): American Ceramic Society; 1988. p. 343-354.

 

N. P. Bansal, D. Boyne, D. E. Farrell, "Doping Directed at the Oxygen Sites in Y1Ba2Cu3O7−δ: The Effect of Sulfur, Fluorine, and Chlorine," J. Supercond, v. 1, p. 417, 1988.

 



Published: August 23, 2024