IC Layout Design I is designed to introduce the student to the integrated circuit design and layout field. This is the first of three courses intended to prepare the student for employment as an IC Layout Designer. The student will be introduced to the integrated circuit design and manufacturing process, CMOS technology basics, symbols and schematics of basic circuits and their behavior, layout design concepts / technique and the use of Cadence Virtuoso Layout Editor, basic Unix commands and Unix environment.

Text:

• IC Layout Basics – Christopher Saint and Judy Saint – required.
• CMOS IC Layout: Concepts, Methodologies, and Tools, Dan Clein – recommended but not required.

 Tools/Materials:

Color pencils, sharpener, eraser, engineering notepad or graph paper (10 sq per in), 1in 3-ring binder, and a notebook.

Prerequisites:

• DFTG 1409 –    Basic Computer Aided Drafting
• DFTG 1458 –    Electrical/Electronic Drafting (or instructor approval)
• HART 1401 –   Basic Electricity Principles (can be taken concurrently)
• CETT 1425 –    Digital Fundamentals (recommended)
• ITSC 1307 –     Unix Operating System I (recommended)         

Exams: There will be a mid-term and a final exam.

Grade Determination:

• Final Exam:                 25% of Final Grade
• Daily Work:                  75% of Final Grade

The Daily Work will consist of homework, assigned layout exercises, class exercises and possible quizzes. Grades will reflect the quality of the work performed within the assigned time period. Late assignments will receive a 10 points (out of 100) penalty for each class period late.

Final Grade:

•      - A -                          =>90%
•      - B -                         80% - 89%
•      - C -                         70% - 79%
•      - D -                         60% - 69%
•      - F -                         < 60%

The reading assignments will be assigned from either the text book or will be given to the students by handout. It is very essential for the students to complete the reading assignment and most importantly to complete their homework the get themselves ready for each and every class session.

Cadence Drawing Assignments:

• Inverter
• Multi-leg P-channel transistor
• Minimum size P-channel transistor
• Two input NOR
• Three input NAND
• Transmission gate
• Flip-flop
• Shift register
• Latch
• Tri-state buffer
• Bonding pad
• Input protection
• Input buffer
• Complex logic gates
• Chip assembly project

Class 1.

• Lecture:
  • Introductions - Explanation and discussion of Syllabus.
• Assignment:
  • Read handout on the Intro IC Layout Design.

Class 2.

• Lecture:
  • Semiconductor industry history and trends. How an idea becomes a product. Circuit symbols and integrated circuit concepts
  • Unix, vi Editor
• Assignment:
  • Read IC 1 Design Rule
  • Hand draw via e-cells
  • Unix vi labs

 Class 3.

• Lecture:
  • Introduction to PMOS and NMOS transistor
  • Setup and use of the Cadence Virtuoso layout editing tool. All students will log on and perform functions to introduce the capabilities of this design tools.
• Assignment:
  • Layout inv40_30 on engineering graph
  • Layout via e-cells and startcell

 Class 4.

• Lecture:
  • Lecture on inverter logic gate
  • Cadence Bindkeys
• Assignment:
  • Inv40_30

 Class 5.

• Lecture:
  • Schematic to layout process and the concept of layout design rules
  • Discussion on additional transistor variations. Multi-leg PMOS / NMOS transistor.
  • Notching / Folding Layout
• Assignment:
  • pmos_80
  • nmos_60

 Class 6.

• Lecture:
  • Lecture on Design Rule Check DRC.
  • Cadence print out a layout / schematic view.
• Assignment:
  • Continue to work on un-finished assignments

 Class 7.

• Lecture:
  • Parallel and serial transistors
  • 2-input NOR2 logic gate
• Assignment:
  • nor2 logic gate layout

 Class 8.

• Lecture:
  • 3-input NAND3 logic gate.
• Assignment:
  • nand3 logic gate  layout

 Class 9.

• Lecture:
  • Transmission T-Gate
• Assignment:
  • Tgate layout

 Class 10.

• Lecture:
  • Flip flop circuit
  • Into to Stick Diagram
  • Stick diagram of a flip-flop
• Assignment:
  • Flip flop layout

 Class 11.

• Lecture:
  • More on flip flop layout
• Assignment:
  • Shift registor layout

 Class 12.

• Lecture:
  • Layout VS Schematic LVS
  • Stick diagram of shift resistor circuit
• Assignment:
  • Continue to work on un-finished assignments

 Class 13.

• Lecture:
  • More on layout of a shift resistor
  • More in depth of LVS
• Assignment:
  • Continue to work on un-finished assignments.

 Class 14.

• Lecture:
  • Reversed engineering
• Assignment:
  • Continue to work on un-finished assignments.

 Class 15.

• Lecture:
  • Midterm review
• Assignment:
  • Latch circuit

 Class 16.

• Lecture:
  • Midterm Exam.
• Assignment:
  • Continue to work on un-finished assignments.

 Class 17.

• Lecture:
  • Go over mid-term exam.
  • Layout of latch circuit.
• Assignment:
  • Complex circuit AOI / OAI

 Class 18.

• Lecture:
  • Complex circuits AOI and OAI
• Assignment:
  • Continue to work on un-finished assignments.

 Class 19.

• Lecture:
  • Tri-state buffer circuit
  • Guard rings
• Assignment:
  • Tri-state tribuf layout

 Class 20.

• Lecture:
  • More on tri-state buffer and guarding layout
• Assignment:
  • Bonding pads
  • Input buffer

 Class 21.

• Lecture:
  • I/O pads layout and input buffer
• Assignment:
  • Input protection

 Class 22.

• Lecture:
  • Input protection of an I/O pad
  • Layout of a resistor
• Assignment:
  • Continue to work on un-finished assignments

 Class 23.

• Lecture:
  • More on layout of input buffer and input protection of I/O pads
• Assignment:
  • Continue to work on un-finished assignments

 Class 24.

• Lecture:
  • Intro to Chip assembly.
• Assignment:
  • Continue to work on un-finished assignments

 Class 25.

• Lecture:
  • Chip_top
• Assignment:
  • Final project “chip”

 Class 26.

• Lecture:
  • Chip_bot
• Assignment:
  • Continue to work on un-finished assignments

 Class 27.

• Lecture:
  • Chip assembly: scribes, edge seal, chip guard rings
• Assignment:
  • Continue to work on un-finished assignments

 Class 28.

• Lecture:
  • Chip corners
• Assignment:
  • Continue to work on final project

 Class 29.

• Lecture:
  • Final project chip continued
• Assignment:
  • Continue to work on final project

 Class 30.

• Lecture:
  • Final project chip continued
• Assignment:
  • Continue to work on final project

 Class 31.

• Lecture:
  • Final Exam Review
• Assignment:
  • Continue to work on final project.

 Class 32.

• Final Exam
• Assignment:
  • Last day to turn in all the assignment and the final project.

At the completion of this course, the student will have demonstrated the ability to:

• Recognize schematic design symbols basic logic gates, PMOS/NMOS devices.
• Recognize the components in the CMOS transistor cross section.
• Understand the design schematics and use it to layout shapes using Cadence Virtuoso.
• Understand what Design Rule Check DRC verification is for, and how to apply its requirements to layout the IC circuits, and how to clean up DRC.
• Understand what Layout Vs Schematic LVS is for and how to debug LVS using Calibre tool. 
• Best layout techniques which include:

o    Fold gates when applicable

o   Share diffusion where appropriate

o   Minimize transistor drain area

o   Properly interconnect circuit nodes with metal lines of sufficient dimension to carry the current load

o   Maximize contact and via cuts as appropriate

o   Minimize the area required for a given circuit

o   Insure sufficient substrate and well ties exist

o   Place text in the design as required by the design schematic

o   Translate resistor values to appropriate layout dimensions

o   Efficiently utilize the Cadence design tool to draw circuit layout

o   Utilize design hierarchy to build cells containing sub-cells

o   Recognize the components that are required to build a complete chip